Two-Level Digital Logic Circuit Worksheet Essay Assignment
Order ID:89JHGSJE83839 Style:APA/MLA/Harvard/Chicago Pages:5-10 Instructions:
Two-Level Digital Logic Circuit Worksheet Essay Assignment
Figure 1. Two-Level Digital Logic Circuit
Go to the Multisim (Links to an external site.) website and create a student account using your student email address.
Click on the Create Circuit button in the upper right corner of the page.
On the left side of the page, find the Digital Menu (all the way at the bottom). Place the three digital constants on the grid page. The default names of the constants will be DG1, DG2, etc. Double click on the symbol to change the ID names to A, B, and C. As you can see, there’s a 1 in the slider bar by default. When you click on symbol, a target appears at the bottom. Click on the target to toggle between 0 and 1.
Next, we want to place a two-input NAND gate and route inputs A and B to the inputs of the NAND with a wire. To do so, hover your cursor over the node of the constant until a spool connector appears. Left click once to generate the wire and lead it to the top node of the NAND gate. Left click to establish the wire connection. Do the same to connect input B to the second input of the NAND.
Now place a two-input OR gate to the right of input C. Connect B and C to the inputs of the OR gate.
To the right of both of these gates, place an XNOR gate. Use wires to connect the outputs of the NAND and the OR to the inputs of the XNOR.
Now your circuit is built, but in order to view the output data from the simulation, we must place a digital meter. To place a meter, find the Analysis and Annotation menu on the left, denoted by the green V. We will also need a wire on which to place the output meter. In the Schematic Connectors menu, find the Junction. Drop the junction just to the right of the XNOR and use a wire to connect it to the output node.
Place a digital output meter by selecting the Digital meter. Attach the meter anywhere along the wire from the output of the XNOR to the junction node.
Your circuit is now ready for simulation. Click the Play button in the upper left to begin the simulation. After a few seconds have passed, click the Stop button.
You are now ready to validate your truth table. Start by assigning 0, 0, 0 to inputs A, B, and C. Run the simulation, view the digital output and record it in your truth table:
Name the circuit “Lab 1 Circuit 1” and save the schematic showing the simulated digital output for inputs 0, 0, 0. To save, click on the small grid of 3×3 squares in the top left of the page and go to Export, then select Schematic image. This will download a .png image of your schematic. Be sure to do this step after you have run your simulation so the meter on the saved schematic show output.
Include this image and truth table in your lab report with appropriate labels.
Part 2 – A Three-Level Digital Logic Circuit
Now that we have constructed a two-level digital circuit together, it’s your turn to draw the schematic for a three-level circuit. For the following function:
F = (((B⊕ C) + A)* A)!
Write the truth table in a spreadsheet, include columns for each intermediate step.
Draw the digital logic schematic in Multisim.
Simulate the outputs for each input combination, include your simulated results as a column on the truth table.
Save your schematic and truth table and include in your lab report.
Part 3 – Lab Report
Using either GoogleDocs, Word or the pdf generator of your choice, compile your images into one file.
Be sure to include figure labels for your images in proper MLA format (figure labels centered below schematics and table labels left-justified above the table). Submit via Canvas as lab1yourlastname.pdf. Thanks and let me know if you have any questions!
RUBRIC
Excellent Quality
95-100%
Introduction 45-41 points
The background and significance of the problem and a clear statement of the research purpose is provided. The search history is mentioned.
Literature Support
91-84 points
The background and significance of the problem and a clear statement of the research purpose is provided. The search history is mentioned.
Methodology
58-53 points
Content is well-organized with headings for each slide and bulleted lists to group related material as needed. Use of font, color, graphics, effects, etc. to enhance readability and presentation content is excellent. Length requirements of 10 slides/pages or less is met.
Average Score
50-85%
40-38 points
More depth/detail for the background and significance is needed, or the research detail is not clear. No search history information is provided.
83-76 points
Review of relevant theoretical literature is evident, but there is little integration of studies into concepts related to problem. Review is partially focused and organized. Supporting and opposing research are included. Summary of information presented is included. Conclusion may not contain a biblical integration.
52-49 points
Content is somewhat organized, but no structure is apparent. The use of font, color, graphics, effects, etc. is occasionally detracting to the presentation content. Length requirements may not be met.
Poor Quality
0-45%
37-1 points
The background and/or significance are missing. No search history information is provided.
75-1 points
Review of relevant theoretical literature is evident, but there is no integration of studies into concepts related to problem. Review is partially focused and organized. Supporting and opposing research are not included in the summary of information presented. Conclusion does not contain a biblical integration.
48-1 points
There is no clear or logical organizational structure. No logical sequence is apparent. The use of font, color, graphics, effects etc. is often detracting to the presentation content. Length requirements may not be met
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Two-Level Digital Logic Circuit Worksheet Essay Assignment